library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench_invertBitGenerator is
end entity testbench_invertBitGenerator;

architecture behavioral of testbench_invertBitGenerator is
component invertBitGenerator is
port(
  A 	: in std_logic_vector(31 downto 0);
  B 	: in std_logic_vector(31 downto 0);
  inv 	: out std_logic
);
end component;
signal A,B : std_logic_vector (31 downto 0);
signal inv : std_logic;
begin
	invGen: invertBitGenerator port map (A,B,inv);
	testSequence : process is
	begin
		A <= "00001110100001001101001110000100";
		B <= "00000000000000000000000000000100";
		wait for 2 ns;
		if inv/= '0' then 
			  ASSERT false
			  REPORT " Hamming distance err 1"
			  SEVERITY failure;
		end if;
		
		A <= "11111111111111111100001000100110";
		B <= "00010000100000100001000000000001";
		wait for 2 ns;
		if inv/= '1' then 
			  ASSERT false
			  REPORT " Hamming distance err 2"
			  SEVERITY failure;
		end if;	
	end process testSequence;
end architecture behavioral;
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench_busInvertCoder is
end entity testbench_busInvertCoder;

architecture behavioral of testbench_busInvertCoder is
component busInvertCoder is
port(
  clk	: in std_logic;
  reset	: in std_logic;
  A 	: in std_logic_vector(31 downto 0);
  B 	: out std_logic_vector(32 downto 0)
);
end component;
signal clk,reset : std_logic;
signal A : std_logic_vector(31 downto 0);
signal B : std_logic_vector(32 downto 0);
constant clkPeriod    : time := 0.1 us;
begin
	bic : busInvertCoder port map (clk,reset,A,B);
	clk_gen: process is
	begin
		clk <= '0';
		wait for clkPeriod/2;
		clk <= '1';
		wait for clkPeriod/2;
	end process clk_gen;
	
	testSequence : process is
	begin
		reset <= '1';
		wait for clkPeriod;
		reset <= '0';
		
		A <= "00001110100001001101001110000100";
		wait for clkPeriod;
		if B/= '0'& A then 
			  ASSERT false
			  REPORT " Hamming distance err 1"
			  SEVERITY failure;
		end if;
		
		A <= "11111111111111111100001000100110";
		wait for clkPeriod;
		if B/= '1'& not(A) then 
			  ASSERT false
			  REPORT " Hamming distance err 2"
			  SEVERITY failure;
		end if;	
		
		A <= "00001110100001001101001110000000";
		wait for clkPeriod;
		if B/= '0'& A then 
			  ASSERT false
			  REPORT " Hamming distance err 3"
			  SEVERITY failure;
		end if;	
		
	end process testSequence;
end architecture behavioral;
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench_busInvertDecoder is
end entity testbench_busInvertDecoder;

architecture behavioral of testbench_busInvertDecoder is
component busInvertDecoder is
port(
  clk	: in std_logic;
  B 	: in std_logic_vector(32 downto 0);
  A 	: out std_logic_vector(31 downto 0)
);
end component;
signal clk : std_logic;
signal A : std_logic_vector(31 downto 0);
signal B : std_logic_vector(32 downto 0);
constant clkPeriod    : time := 0.1 us;
begin
	bic : busInvertDecoder port map (clk,B,A);
	clk_gen: process is
	begin
		clk <= '0';
		wait for clkPeriod/2;
		clk <= '1';
		wait for clkPeriod/2;
	end process clk_gen;
	
	testSequence : process is
	begin
				
		B <= '0' & "00001110100001001101001110000100";
		wait for clkPeriod;
		if A/= "00001110100001001101001110000100" then 
			  ASSERT false
			  REPORT " Hamming distance err 1"
			  SEVERITY failure;
		end if;
		
		B <= '1' & not("11111111111111111100001000100110");
		wait for clkPeriod;
		if A/= "11111111111111111100001000100110" then 
			  ASSERT false
			  REPORT " Hamming distance err 2"
			  SEVERITY failure;
		end if;	
		
		B <= '0' & "00001110100001001101001110000000";
		wait for clkPeriod;
		if A/= "00001110100001001101001110000000" then 
			  ASSERT false
			  REPORT " Hamming distance err 3"
			  SEVERITY failure;
		end if;	
		
	end process testSequence;
end architecture behavioral;
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench_clockGenerator is
end entity testbench_clockGenerator;

architecture behavioral of testbench_clockGenerator is
component clockGenerator is
port(
  mainClk 	: in std_logic;
  reset		: in std_logic;
  deadline 	: in std_logic_vector(1 downto 0);
  clk 		: out std_logic
);
end component;

signal mainClk,clk,reset	: std_logic;
signal deadline 			: std_logic_vector(1 downto 0);
constant clkPeriod  		: time := 0.1 us;
begin
	clkGen : clockGenerator port map(mainClk,reset,deadline,clk);
	
	clk_main: process is
	begin
		mainClk <= '0';
		wait for clkPeriod/2;
		mainClk <= '1';
		wait for clkPeriod/2;
	end process clk_main;
	
	testSequence : process is
	begin
		reset <= '1';
		wait for clkPeriod;
		reset <= '0';
		deadline <= "00";
		wait for 8*clkPeriod;
		
		deadline <= "01";
		wait for 8*clkPeriod;
		
		deadline <= "10";
		wait for 8*clkPeriod;
		
		deadline <= "11";
		wait for 8*clkPeriod;
		
		deadline <= "00";
		wait for 8*clkPeriod;
		
		reset <= '1';
		wait for 8*clkPeriod;
	end process testSequence;
end architecture behavioral;
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity testbench_decoder4x16 is
end entity testbench_decoder4x16;

architecture behavioral of testbench_decoder4x16 is
component decoder4x16 is
port(
  Op   : in std_logic_vector(3 downto 0);
  en   : out std_logic_vector(15 downto 0)
);
end component;

signal Op : std_logic_vector(3 downto 0);
signal en : std_logic_vector(15 downto 0);
begin
	decode: decoder4x16 port map(Op,en);
	
	testSequence : process is
	begin
		Op <= "0100";
		wait for 2 ns;
		if en/= "0000000000010000" then 
			  ASSERT false
			  REPORT " Decoder err 1"
			  SEVERITY failure;
		end if;	
		
		Op <= "1100";
		wait for 2 ns;
		if en/= "0001000000000000" then 
			  ASSERT false
			  REPORT " Decoder err 1"
			  SEVERITY failure;
		end if;	
	end process testSequence;
	
end architecture behavioral;